Depending upon which always block gets triggered first, the second always block may see the updated value or the previous value of a. In the above code, signal a is being updated through the first always block, while it’s also being read through the second always block. Combinational Read-Write Race always (b, c) a = b & c always (b ) o = a ^ b Simulation event regions for system verilog Read-Write Race Read-Write race occurs when a signal is being read in one always block at the same time as being updated in another always block. Please go through the document attached below to have a better understanding of Verilog/SV simulation event schedule.
By its definition, race implies that there could be multiple interpretations of the same HDL, and, all of them are correct.
#Post synthesis simulation modelsim altera code
Race means same HDL code exhibiting two or more possible behaviors, both of which are correct as per the language interpretation. What is Race in the context of HDL simulation?.